1. Field of the Invention
The present invention relates to an ignition system for a multiple cylinder internal combustion engine, wherein an ignition timing operation is carried out in a single circuit and the results of the operation is distributed to the respective cylinders.
2. Discussion of Background
FIG. 3 is a schematic circuit diagram showing a conventional internal combustion engine ignition timing control system. In FIG. 3, reference numeral 1 designates the power generation winding of a permanent-magnet generator which is driven by an internal combustion engine (not shown). The power generation winding has one end connected to the primary winding 6 of a first cylinder ignition coil 5 through a diode 2 and a thyristor 3 for the first cylinder, and to the primary winding 8 of a second cylinder ignition coil 7 through the diode 2 and a second cylinder thyristor 4. The power generation winding has the other end grounded. Reference numeral 9 designates an ignition capacitor which is connected between ground and the junction of the diode 2 and the thyristors 3 and 4. Reference numerals 10 and 11 designate the secondary windings for the first cylinder ignition coil 5 and the second cylinder ignition coil 7, respectively. The ignition coils 5 and 7 are connected to ignition plugs 12 and 13, respectively. Reference numerals 14 and 15 designate resistors which are connected between the gates and the cathodes of the thyristors 3 and 4, respectively. Reference numeral 16 designates an electrical power source which is constituted by a series combination of a diode 17, a resistor 18 and a zener diode 19 with respect to the output of the power generation winding 1, and a capacitor 20 connected in parallel with the zener diode 19.
Reference numerals 21 and 22 designate a first cylinder signal winding and second cylinder signal winding, respectively. The signal windings have their respective one ends connected to the cathodes of diodes 23 and 24, respectively. The signal windings have their respective other ends grounded. The anodes of the diodes 23 and 24 are respectively connected to the bases of transistors 29 and 30 through a CR bias network comprising a capacitor 25 and resistor 26, and through a CR bias network comprising a capacitor 27 and a resistor 28. To the bases of the transistors are connected the electrical power source through resistors 31 and 32, respectively. The collectors of the transistors 29 and 30 are connected to the power source through resistors 33 and 34, respectively. The collectors are also connected to the reset input terminals S of flip flops (hereinbelow, referred to as FF) 35 and 36. The emitters of the transistors are grounded. The set input terminal S of the FF 35 is connected to the reset input terminal R of FF 36. The set input terminal S of the FF 36 is connected to the reset input terminal R of the FF 35. The set input terminals S are connected to the input terminal of an ignition timing operating circuit 39 through diodes 37 and 38, respectively. The ignition timing operating circuit 39 has the output terminal connected to the non-inverting inputs of operational amplifiers 41 and 42 for the first and the second cylinder through a resistor 40. The operational amplifiers 41 and 42 have the inverting input terminals connected to the output terminals Q the FFs 35 and 36. The operational amplifier 41 has the output terminal connected to the gate of the thyristor 3 through a capacitor 43 and a diode 44. The operational amplifier 42 has the output terminal connected to the gate of the thyristor 4 through a capacitor 45 and a diode 46. Reference numerals 47 and 48 designate diodes, respectively, which are connected between ground and the junction of the capacitor 43 and the diode 44, and between ground and the junction of the capacitor 45 and the diode 46, respectively. Reference numeral 49 designates a resistor which is connected between ground and the non-inverting input terminals of the operational amplifiers 41 and 42.
In operation, the signal windings 21 and 22 output ignition signals shown in FIG. 4 at (a) and (b) in synchronism with the rotation of the engine. The waveshapes at points a-j in FIG. 3 are shown in FIG. 4 at (a)-(j). The transistors 29 and 30 are driven to cutoff by the ignition signals. As a result, the ignition signal by the signal winding 21 makes the FF 35 set and the FF 36 reset. The ignition signal by the signal winding 22 makes the FF 35 reset and the FF 36 set. In this way, the outputs Q of the FFs 35 and 36 form the waveshapes shown in FIG. 4 at (c) and (d), respectively. At the same time, the set signals to FFs 35 and 36 are inputted to the ignition timing operating circuit 39 through the diodes 37 and 38, respectively, as shown in FIG. 4 at (e). The ignition timing operating circuit carries out a predetermined ignition timing operation based on such inputs, outputting an ignition timing control signal for the two cylinders as shown in FIG. 4 at (f). In the period between the ignition signal of the signal winding 21 and that of the signal winging 22, the ignition timing control signal applied to the operational amplifier 41 causes the operational amplifier 41 to output a signal from its output terminal in synchronism with the ignition timing control signal because the output of the FF 35 is at a low level in that period. In the period between the ignition signal of the signal winding 22 and the ignition signal of the signal winding 21, even if the ignition timing control signal is applied to the operational amplifier 41, the operational amplifier 41 does not output the ignition signal from its output terminal. This is because the output of the FF 35 is at a high level in that period. That is to say, the ignition timing control signal for the first cylinder allows the operational amplifier 41 to output the ignition signal as shown in FIG. 4 at (g). Because the output level of the FF 36 is opposite to that of the FF 35, the output of the operational amplifier 42 becomes an ignition signal in synchronism with the ignition timing control signal for the second cylinder as shown in FIG. 4 at (h) like the operational amplifier 41 for the first cylinder. In this way, the ignition timing control signals for the two cylinders are distributed to the respective cylinders. The ignition signals which have been outputted from the operational amplifiers 41 and 42 are differentiated by the capacitors 43 and 45, respectively, to become signals as shown in FIG. 4 at (i) and (j), and the signals so obtained are applied to the gates of the thyristors 3 and 4, respectively. When the thyristors 3 and 4 are driven to conduction, the charge stored in the ignition capacitor 9 is discharged to the primary windings 6 and 8 of the ignition coils 5 and 7, thereby inducing a high voltage in the respective secondary windings 10 and 11. As a result, spark discharge is produced in the ignition plugs 12 and 13.
The conventional internal combustion engine ignition system carries out the ignition timing operation in the single ignition timing operating circuit 39 in this way, and distributes ignition timing control signals which have been outputted as the result of the ignition timing operation. There is a problem that the number of parts is great, in particular that the number of the FFs 35 and 36 should correspond to the number of cylinders to perform such distribution.